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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xr16c2850 2.97v to 5.5v dual uart with 128-byte fifos november 2005 rev. 2.1.3 general description the xr16c2850 1 (2850) is an enhanced dual universal asynchronous receiver and transmitter (uart). enhanced features include 128 bytes of tx and rx fifos, programmable tx and rx fifo trigger level, fifo level counters, automatic (rts/ cts) hardware and (xon/xoff) software flow control, automatic rs-485 half duplex direction control output and data rates up to 6.25 mbps at 5v and 8x sampling clock. onboard status registers provide the user with operational status and da ta error flags. an internal loopback capability allows system diagnostics. the 2850 has a full modem interface and can operate at 2.97v to 5.5v and is pin-to-pin compatible to exar?s st16c2550 and xr16c2750 except the 48-tqfp package. the 2850 register set is compatible to the industry standard st16c2550 and is available in 48- pin tqfp and 44-pin plcc packages. n ote : 1 covered by u.s. patent #5,649,122 and #5,949,787 applications ? portable appliances ? telecommunication network routers ? ethernet network routers ? cellular data devices ? factory automation and process controls features added feature in devices with a top mark date code of "f2 yyww" and newer: 5v tolerant inputs 0 ns address hold time (t ah ) ? pin-to-pin compatible and fu nctionally compatible to exar?s st16c2550 and xr16l2750 and ti?s tl16c752b in the 48-tqfp package ? pin-alike exar?s xr16l2750 and st16c2550 48- tqfp package but with additional clk8/16, clksel and hdcntl inputs ? two independent uart channels register set compatible to 16c550 up to 6.25 mbps at 5v, and 4 mbps at 3.3v transmit and receive fifos of 128 bytes programmable tx and rx fifo trigger levels transmit and receive fifo level counters automatic hardware (rts/cts) flow control selectable auto rts flow control hysteresis automatic software (xon/xoff) flow control auto rs-485 half-duple x direction control wireless infrared (irda 1.0) encoder/decoder full modem interface ? device identification and revision ? crystal oscillator or external clock input ? industrial and commercial temperature ranges ? 48-tqfp and 44-plcc packages f igure 1. xr16c2850 b lock d iagram xtal1 xtal2 crystal osc/buffer txa, rxa, dtra#, dsra#, rtsa#, dtsa#, cda#, ria#, op2a# 8-bit data bus interface uart channel a 128 byte tx fifo 128 byte rx fifo brg ir endec tx & rx uart regs 2.97v to 5.5v vcc gnd txb, rxb, dtrb#, dsrb#, rtsb#, ctsb#, cdb#, rib#, op2b# uart channel b (same as channel a) a2:a0 d7:d0 csa# csb# inta intb iow# ior# reset txrdya# txrdyb# rxrdya# rxrdyb# clk8/16 clksel hdcntl#
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 2 f igure 2. p in o ut a ssignment ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr16c2850cj 44-lead plcc 0c to +70c active xr16c2850cm 48-lead tqfp 0c to +70c active xr16c2850ij 44-lead plcc -40c to +85c active xr16c2850im 48-lead tqfp -40c to +85c active 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# csa# csb# nc xtal1 xtal2 iow# cdb# gnd rxrdyb# ior# dsrb# rib# rtsb# ctsb# clk8/16 reset dtrb# dtra# rtsa# op2a# rxrdya# inta intb a0 a1 a2 clksel d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# hdcntl# xr16c2850 48-pin tqfp 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# csa# csb# reset dtrb# dtra# rtsa# op2a# rxrdya# inta intb a0 a1 a2 xtal1 xtal2 iow# cdb# gnd rxrdyb# ior# dsrb# rib# rtsb# ctsb# d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# xr16c2850 44-pin plcc
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 3 pin descriptions n ame 44-plcc p in # 48-tqfp p in # t ype d escription data bus interface a2 a1 a0 29 30 31 26 27 28 i address data lines [2:0]. these 3 a ddress lines select one of the inter - nal registers in uart channel a/b during a data bus transaction. d7 d6 d5 d4 d3 d2 d1 d0 9 8 7 6 5 4 3 2 3 2 1 48 47 46 45 44 i/o data bus lines [7:0] (bidirectional). ior# 24 19 i input/output read strobe (active low). the falling edge instigates an internal read cycle and retrieves the da ta byte from an internal register pointed to by the address lines [a2:a0]. the data byte is placed on the data bus to allow the host processor to read it on the rising edge. iow# 20 15 i input/output write strobe (active low). the falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. csa# 16 10 i uart channel a select (active low) to enable uart channel a in the device for data bus operation. csb# 17 11 i uart channel b select (active low) to enable uart channel b in the device for data bus operation. inta 33 30 o uart channel a interrupt output. th e output state is defined by the user through the software setting of mcr[3]. inta is set to the active mode and op2a# output is low when mcr[3] is set to a logic 1. inta is set to the three state mode and op2a# is high when mcr[3] is set to a logic 0 (default). s ee mcr[3]. if this output is not used, leave it unconnected. intb 32 29 o uart channel b interrupt output. th e output state is defined by the user through the software setting of mcr[3]. intb is set to the active mode and op2b# output is low when mc r[3] is set to a logic 1. intb is set to the three state mode and op2b# is high when mcr[3] is set to a logic 0 (default). s ee mcr[3]. if this output is not used, leave it unconnected. txrdya# 1 43 o uart channel a transmitter re ady (active low). the output provides the tx fifo/thr status for transmit channel a. see table 2 . if this output is not us ed, leave it unconnected. rxrdya# 34 31 o uart channel a receiver ready (activ e low). this output provides the rx fifo/rhr status for receive channel a. see table 2 . if this output is not used, leave it unconnected. txrdyb# 12 6 o uart channel b transmitter ready (active low). the output provides the tx fifo/thr status fo r transmit channel b. see table 2 . if this output is not used, leave it unconnected.
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 4 rxrdyb# 23 18 o uart channel b receiver ready (activ e low). this output provides the rx fifo/rhr status for receive channel b. see table 2 . if this output is not used, leave it unconnected. modem or serial i/o interface txa 13 7 o uart channel a transmit data or infrared encoder data. standard transmit and receive interface is en abled when mcr[6] = 0. in this mode, the tx signal will be high during reset or idle (no data). infrared irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared encoder/ decoder interface islow. if this ou tput is not used, leave it uncon - nected. rxa 11 5 i uart channel a receive data or infrared receive data. normal receive data input must idle high. the infrared receiver pulses typically idles low but can be inverted by software control prior going in to the decoder, see mcr[6] and fctr[2]. if this pin is not used, tie it to vcc or pull it high via a 100k ohm resistor. rtsa# 36 33 o uart channel a request-to-send (act ive low) or general purpose out - put. this output must be asserted prior to using auto rts flow control, see efr[6], mcr[1], fctr[1:0], emsr[5:4] and ier[6]. for auto rs485 half-duplex direction control, se e fctr[3]. if this output is not used, leave it unconnected. ctsa# 40 38 i uart channel a clear-to-send (active low) or general purpose input. it can be used for auto cts flow co ntrol, see efr[7], and ier[7]. this input should be connected to vcc when not used. dtra# 37 34 o uart channel a data-terminal-ready (active low) or general purpose output. if this out put is not used, leave it unconnected. dsra# 41 39 i uart channel a data-set-ready (activ e low) or general purpose input. this input should be connected to vcc when not used. cda# 42 40 i uart channel a carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. ria# 43 41 i uart channel a ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. op2a# 35 32 o output port 2 channel a - the output state is defined by the user and through the software setting of mcr[3] . inta is set to the active mode and op2a# output is low when mcr[3] is set to a logic 1. inta is set to the three state mode and op2a# is high when mcr[3] is set to a logic 0. see mcr[3]. this output can only be used as a general pur - pose output when interrupts are not used, otherwise it will disturb the inta output functionality. if this output is not used, leave it uncon - nected. txb 14 8 o uart channel b transmit data or infrared encoder data. standard transmit and receive interface is en abled when mcr[6] = 0. in this mode, the tx signal will be high during reset or idle (no data). infrared irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared encoder/ decoder interface is low. if this output is not us ed, leave it uncon - nected. n ame 44-plcc p in # 48-tqfp p in # t ype d escription
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 5 rxb 10 4 i uart channel b receive data or infrared receive data. normal receive data input must idle high. the infrared receiver pulses typically idles low but can be inverted by software control prior going in to the decoder, see mcr[6] and fctr[2]. if this pin is not used, tie it to vcc or pull it high via a 100k ohm resistor. rtsb# 27 22 o uart channel b request-to-send (act ive low) or general purpose out - put. this port must be asserted prior to using auto rts flow control, see efr[6], mcr[1], fctr[1:0], emsr[5:4] and ier[6]. for auto rs485 half-duplex direction control, see fctr[3] and emsr[3]. if this output is not used, leave it unconnected. ctsb# 28 23 i uart channel b clear-to-send (active low) or general purpose input. it can be used for auto cts flow co ntrol, see efr[7], and ier[7]. this input should be connected to vcc when not used. dtrb# 38 35 o uart channel b data-terminal-ready (active low) or general purpose output. if this output is not us ed, leave it unconnected. dsrb# 25 20 i uart channel b data-set-ready (activ e low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. cdb# 21 16 i uart channel b carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. rib# 26 21 i uart channel b ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. op2b# 15 9 o output port 2 channel b - the output state is defined by the user and through the software setting of mcr[3]. intb is set to the active mode and op2b# output is low when mcr[3] is set to a logic 1. intb is set to the three state mode and op2b# is high when mcr[3] is set to a logic 0. see mcr[3]. this output can only be used as a general pur - pose output when interrupts are not used, otherwise it will disturb the intb output functionality. if this output is not used, leave it uncon - nected. ancillary signals xtal1 18 13 i crystal or external clock input. xtal2 19 14 o crystal or buffered clock output. hdcntl# - 37 i rs-485 half duplex directional control for channel a and b (active low). connect to vcc for normal rts# function and connect to gnd for rs- 485 half duplex direction control. rts# pin goes low for transmit and high for receive during rs-485 mode. this pin is wire ?or-ed? with fctr[3]. if this pin is connected to vcc, the function of the rts# pin can be controlled via fctr[3]. if this pin is connected to gnd, the rts# pin will always be the rs-485 half duplex direction control and can not be controlled via fctr[3]. see fctr[3]. n ame 44-plcc p in # 48-tqfp p in # t ype d escription
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 6 pin type: i=input, o=output, i/o= input/output, od=output open drain. clksel - 25 i clock pre-scaler select. connect to vcc for divide by 1 and gnd for divide by 4. mcr[7] can override th e state of this pin following reset or initialization. see figure 6 and mcr[7]. clk8/16 - 24 i transmit/receive data sampling rate. connect to vcc for normal 16x sampling clock (standard baud rates) or gnd for 8x sampling clock to double the standard baud rates. reset 39 36 i reset (active high) - a longer than 40 ns high pulse on this pin will reset the internal registers and all outputs. the uart transmitter output will be held at logic 1, the receiver input will be ignored and outputs are reset during reset period (see table 16 ). vcc 44 42 pwr 2.97v to 5.5v power supply. all inputs are 5v tolerant for devices with top mark date code of "f2 yyww" and newer. gnd 22 17 pwr power supply common, ground. n.c. none 12 no connection. n ame 44-plcc p in # 48-tqfp p in # t ype d escription
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 7 1.0 product description the xr16c2850 (2850) integrates the functions of 2 enhanced 16c550 universal asynchrounous receiver and transmitter (uart). each uart is independently c ontrolled having its own set of device configuration registers. the configuration registers set is 16550 ua rt compatible for control, status and data transfer. additionally, each uart channel has 128-bytes of tran smit and receive fifos, au tomatic rts/cts hardware flow control with hysteresis contro l, automatic xon/xoff and special character software flow control, programmable transmit and receive fifo trigger levels , fifo level counters, infrared encoder and decoder (irda ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 6.25 mbps with 8x sampling clock rate (available only in th e 48-pin tqfp package) or 3.125mbps in the 16x rate. the xr16c2850 is a 5v and 3.3v device. the 2850 is fabricated with an advanced cmos process. enhanced features the 2850 duart provides a solution that supports 128 bytes of transmit and receive fifo memory, instead of 64 bytes provided in the xr16l2750 and 16 bytes in the st16c2550, or one byte in the st16c2450. the 2850 is designed to work with high performance da ta communication systems, that require fast data processing time. increased performance is realized in the 2850 by the larger transmit and receive fifos, fifo trigger level control, fifo level counters and automati c flow control mechanism. this allows the external processor to handle more networking tasks within a gi ven time. for example, the st16c2550 with a 16 byte fifo, unloads 16 bytes of receive data in 1.53 ms (this example uses a ch aracter length of 11 bits, including start/stop bits at 115.2kbps). this means the external cpu will have to service the receive fifo at 1.53 ms intervals. however with the 128 byte fifo in t he 2850, the data buffer will not require unloading/loading for 12.2 ms. this increases the service interval giving the external cpu additional time for other applications and reducing the overall uart interrupt se rvicing time. in addition, the program mable fifo level trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel system. the combination of the above greatly reduces the cpu?s bandwidth requirement, increases perfor mance, and reduces power consumption. the 2850 supports a half-duplex output direction control signaling pin, rts# a/b, to enable and disable the external rs-485 transceiver operation. it automatically s witches the logic state of th e output pin to the receive state after the last stop-bit of the last character has been shifted out of the transmitter. after receiving, the logic state of the output pin switches back to the transmit stat e when a data byte is loaded in the transmitter. the auto rs-485 direction control pin is no t activated after reset. to activate the direction control function, user has to set fctr bit-3 to ?1 ?. this pin is normally high for re ceive state, low for transmit state. data rate the 2850 is capable of operation up to 3.125 mbps at 5v with 16x internal sampling clock rate, and 6.25 mbps at 5v with 8x sampling clock rate (available only on the 48-pin package). the device can operate with an external 24 mhz crystal on pins xtal1 and xtal2, or external clock source of up to 50 mhz on xtal1 pin. with a typical crystal of 14.7456 mhz and through a software option, the user can set the prescaler bit for data rates of up to 1.84 mbps. the rich feature set of the 2850 is available through th e internal registers. automa tic hardware/software flow control, selectable transmit and receive fifo trigger levels, selectable tx and rx baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. following a power on reset or an external reset, the 2850 is software compatible with previous generation of uarts, 16c2450, 16c2550 and 16l2750.
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 8 2.0 functional descriptions 2.1 cpu interface the cpu interface is 8 data bits wide with 3 address li nes and control signals to execute data bus read and write transactions. the 2850 data interface supports the in tel compatible types of cpus and it is compatible to the industry standard 16c550 uart. no clock (oscillator nor external clock) is requir ed to operate a data bus transaction. each bus cycle is asynchronous using cs#, ior# and iow# signals. both uart channels share the same data bus for host operations. t he data bus interconnections are shown in figure 3 . . 2.2 device reset the reset input resets the internal registers and the seri al interface outputs in both channels to their default state (see ta b l e 16 ). an active high pulse of lo nger than 40 ns dura tion will be required to activate the reset function in the device. 2.3 device identification and revision the xr16c2850 provides a device identification code and a device revision code to distinguish the part from other devices and revisions. to read the identification code from the part, it is required to set the baud rate generator regist ers dll and dlm both to 0x00. now reading the content of th e dlm will provide 0x12 for the xr16c2850 and reading th e content of dll will provide th e revision of the part; for example, a reading of 0x01 means revision a. 2.4 channel a and b selection the uart provides the user with the capability to bi-directionally tr ansfer information be tween an external cpu and an external serial communication device. a lo gic 0 on chip select pins, csa# or csb#, allows the user to select uart channel a or b to configure, se nd transmit data and/or unload receive data to/from the uart. selecting both uarts can be useful during power up initialization to write to t he same internal registers, but do not attempt to read from both uarts simultaneous ly. individual channel select functions are shown in table 1 . f igure 3. xr16c2850 d ata b us i nterconnections vcc vcc op2a# dsra# ctsa# rtsa# dtra# rxa txa ri a# cda# op2b# dsrb# ctsb# rtsb# dtrb# rxb txb ri b# cdb# gnd a0 a1 a2 uart_csa# uart_csb# ior# iow# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart _i nt b uart _i nt a intb inta rxrdya# txrdya# rxrdya# t xrdya# rxrdyb# txrdyb# rxrdyb# t xrdyb# uart_reset reset serial i nt erf ace of rs- 232, rs- 485 serial interface of rs- 232, rs-485 2750int
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 9 2.5 channel a and b internal registers each uart channel in the 2850 has a set of enhanced registers for control, monitoring and data loading and unloading. the configuration register set is compatib le to those already available in the standard single 16c550 and dual st16c2550. these r egisters function as data holding regi sters (thr/rhr), interrupt status and control registers (isr/ier), a fi fo control register (fcr), receive lin e status and control registers (lsr/ lcr), modem status and control regist ers (msr/mcr), programmable data rate (clock) divisor registers (dll/ dlm), and a user accessible scratchpad register (spr). beyond the general 16c 2550 features and capabilitie s, the 2850 offers enhanced feature registers (emsr, flvl, efr, xon/xoff 1, xon/xoff 2, fctr, trg, fc ) that provide automatic rts and cts hardware flow control, xon/xoff software flow control, automatic rs-485 half-duplex direction output enable/disable, fifo trigger level control, and fifo level counters. all the register functions are discussed in full detail later in ?section 3.0, uart internal registers? on page 21 . 2.6 dma mode the device does not support direct memory access. th e dma mode (a legacy term) in this document doesn?t mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the state of the rxrdy# a/b and txrdy# a/b output pins. the transmit and receive fifo trigger levels provide additional flexibility to the user for block mode operation. the lsr bits 5- 6 provide an indication when the transmitter is empty or has an empty location(s) for more data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3=1). when the transmit and receive fifo are enabled and the dma mode is disabled (fcr bit-3 = 0), the 2850 is placed in single -character mode for data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the programmed trigger level. in this mode, the 2850 sets the txrdy# pin when the transmit fifo becomes fu ll, and sets the rxrdy# pi n when the receive fifo becomes empty. the following table shows their behavior. also see figures 20 through 25 . t able 1: c hannel a and b s elect csa# csb# f unction 1 1 uart de-selected 0 1 channel a selected 1 0 channel b selected 0 0 channel a and b selected t able 2: t able 2txrdy# and rxrdy# o utputs in fifo and dma m ode p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) rxrdy# a/b low = 1 byte high = no data low = at least 1 byte in fifo high = fifo empty high to low transiti on when fifo reaches the trigger level, or timeout occurs. low to high transition when fifo empties. txrdy# a/b low = thr empty high = byte in thr low = fifo empty high = at least 1 byte in fifo low = fifo has at least 1 empty location high = fifo is full
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 10 2.7 inta and intb ouputs the inta and intb interrupt output output changes acco rding to the operating mode and enahnced features setup. table 3 and 4 summarize the operating behavior for the transmitter and receiver. also see figures 20 through 25 . 2.8 crystal oscillator or external clock input the 2850 includes an on-chip oscillator (xtal1 and xta l2) to produce a clock for both uart sections in the device. the cpu data bus does not require this clock for bus operation. the crystal oscillator provides a system clock to the baud rate generators (brg) section found in each of the uart. xtal1 is the input to the oscillator or external clock buffer in put with xtal2 pin being the output. see?programmable baud rate generator? on page 11. f igure 4. t ypical oscillator connections the on-chip oscillator is designed to use an industry standard micropro cessor crystal (p arallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100 ppm frequency tolerance) connected externally between the xtal1 and xtal2 pins (see figure 4 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. t able 3: inta and intb p ins o peration for t ransmitter auto rs485 mode fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) inta/b pin no low = a byte in thr high = thr empty low = fifo above trigger level high = fifo below trigger level or fifo empty inta/b pin yes low = a byte in thr high = transmitter empty low = fifo above trigger level high = fifo below trigger level or transmitter empty t able 4: inta and intb p in o peration f or r eceiver fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) inta/b pin low = no data high = 1 byte low = fifo below trigger level high = fifo above trigger level c1 22-47 pf c2 22-47 pf y1 1.8432 mhz to 24 mhz r1 0-120 ? (optional) r2 500 ? ? 1 ? xtal1 xtal2
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 11 typical oscillator conn ections are shown in figure 4 . for further reading on oscillator circuit please see application note dan108 on exar?s web site. 2.9 programmable baud rate generator a single baud rate generator (brg) is provided for the transmitter and receiver, allowing independent tx/rx channel control. the programmable baud rate generator is capable of operating with a crystal frequency of up to 24 mhz. however, with an external clock input on xtal1 pin and a 2k ohms pull-up resistor on xtal2 pin (as shown in figure 5 ) it can extend its operation up to 50 mhz (3.125 mbps serial data rate and 16x sampling) at room temperature and 5.0v. f igure 5. e xternal c lock c onnection for e xtended d ata r ate each uart also has their own prescaler along wi th the brg. the prescaler is controlled by clksel hardware pin or a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4 and can override the clksel pin following reset. the clock output of the prescaler goes to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 -1) to obtain a 16x sampling rate clock of the serial data rate . the sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. programming the ba ud rate generator regi sters dlm and dll provides th e capability of selecting the operating data rate. table 5 shows the standard data rates availabl e with a 14.7456 mhz crystal or external clock at 16x sampling rate clock rate. a 16x sampling clock is typically used . however, user can select the 8x sampling clock rate mode to double the operating data rate. when using a non-standard data rate crystal or external clock, the divisor value can be calculated for dll/dlm with the following equation. f igure 6. b aud r ate g enerator and p rescaler 2k xtal1 xtal2 r1 vcc external clock vcc gnd xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll and dlm registers prescaler divide by 1 prescaler divide by 4 16x sampling rate clock to transmitter baud rate generator logic
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 12 2.10 transmitter the transmitter section comp rises of an 8-bit transmit shift regist er (tsr) and 128 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x/8x internal clock. a bit time is 16 (8) clock periods (see clk8/1 6 pin description). the transmitter sends the start-bit followed by the number of data bits, inserts the proper pari ty-bit if enabled, and adds the stop-bit(s). the status of the fifo and tsr are reported in the li ne status register (lsr bit-5 and bit-6). 2.10.1 transmit holding re gister (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 128 bytes when fifo operation is enabled by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.10.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a tr ansmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16), with clk8/16 pin = 1 divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 8), with clk8/16 pin = 0 t able 5: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 (d efault ) d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 13 2.10.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 128 bytes of transmit data. the thr empt y flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed trig ger level. the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty. f igure 7. t ransmitter o peration in non -fifo m ode f igure 8. t ransmitter o peration in fifo and f low c ontrol m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x or 8x clock transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below the programmed trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo 16x or 8x clock auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg. txfifo1
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 14 2.11 receiver the receiver section contains an 8-bit receive shift re gister (rsr) and 128 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x/8x clock (clk8/16 pin) for timing. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter st arts counting at the 16x/8x clock rate. after 8 clocks (or 4 if 8x) the start bit period should be at the center of the star t bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the rece iver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are repo rted in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the rece ive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay until it reaches the fifo trigger level. furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. th e rhr interrupt is enabled by ier bit-0. 2.11.1 receive holding regi ster (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 128 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains the first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 9. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x or 8x clock receive data characters data bit validation error tags in lsr bits 4:2
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 15 n ote : table-b selected as trigger table for figure 10 ( table 10 ). 2.12 auto rts (hardware) flow control automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/r esume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 11 ): ? enable auto rts flow control using efr bit-6. ? the auto rts function must be started by asserting rts output pin (mcr bit-1 to logic 1 after it is enabled). with the auto rts functi on enabled, the rts# output pin will not be de-asserted (high) when the receive fifo reaches the progr ammed trigger level, but will be de-asserted when the fifo reaches the next trigger level ( see table 10 ). the rts# output pin will be asserted (low) again after the fifo is unloaded to the next trigger level below the prog rammed trigger level. howeve r, even under these conditi ons, the 2850 will continue to accept data until the receive fifo is full if the remote uart transmitter continues to send data. ? enable rts interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts# pin is de-asserted (high) during auto rts flow control mode: isr bit-5 will be set to logic 1. 2.13 auto rts hysteresis the 2850 has a new feature that provid es flow control trigger hysteresis while maintaining compatibility with the xr16c850, st16c650a and st16c550 family of ua rts. with the auto rts function enabled, an interrupt is genera ted when the receive fifo reaches the prog rammed rx trigger level. the rts# pin will not be forced high (rts off) until the receive fifo reaches the upper limit of the hysteresis level. the rts# pin will return low after the rx fifo is unloaded to the lower limit of the hysteresis level. under the above described conditions, the 2 850 will continue to accept data until the re ceive fifo gets full. the auto rts function is initiated when the rts# out put pin is asserted low (rts on). table 13 shows the complete details for the auto rts# hysteresis le vels. please note that this table is for programmable trigger levels only (table d). the hysteresis values for tables a-c are the next higher and next lower trigger levels in the corresponding table. f igure 10. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) rxfifo1 16x or 8x clock error tags (128-sets) error tags in lsr bits 4:2 128 bytes by 11-bit wide fifo receive data characters fifo trigger=16 example: - rx fifo trigger level selected at 16 bytes (see note below) data fills to 24 data falls to 8 data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-1. rts# re-asserts when data falls below the flow control trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-1.
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 16 2.14 auto cts flow control automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the aut o cts flow control feature is selected to fit specific application requirement (see figure 11 ): ? enable auto cts flow control using efr bit-7. with the auto cts function enabled, the uart will suspend transmission as soon as the stop bit of the character in the transmit shift register has been shifted out. transmission is resumed after the cts# input is re-asserted (low), indicating more data may be sent. ? enable cts interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (high) during auto cts flow control mo de: isr bit-5 will be set to 1. f igure 11. a uto rts and cts f low c ontrol o peration the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into it s fifo. if interrupt service latency is l ong and data is not being unloaded, uarta monitors its receive data fill level to match the upper th reshold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 17 2.15 auto xon/xoff (software) flow control when software flow control is enabled ( see table 15 ), the 2850 compares one or two sequential receive data characters with the programmed xon or xoff-1,2 character value(s). if receive character(s) (rx) match the programmed values, the 2850 will halt transmission (tx) as soon as the current char acter has completed transmission. when a match occurs, the xoff (if enabled vi a ier bit-5) flag will be set and the interrupt output pin will be activated. following a suspen sion due to a ma tch of the xoff character, the 2850 will monitor the receive data stream for a match to the xon-1,2 character. if a match is found, the 2850 will resume operation and clear the flags (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to a logic 0. following reset, any desired xon/xoff value can be used for so ftware flow control. different condit ions can be set to detect xon/xoff characters ( see table 15 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the 2850 compares two consecutive receive ch aracters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmissi ons accordingly. under the above described flow control mechanisms, flow control characters are not placed (sta cked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the 2850 automatically sends an xoff message (when enabled) via the serial tx output to the remote modem. the 2850 sends the xoff-1,2 characters two character times (= time taken to send two characters at the programmed baud rate) after the receive fifo crosses the programmed trigger level (for all trigger tables a-d). to clear this condition, the 2850 will transmit the program med xon-1,2 characters as soon as re ceive fifo is less than one trigger level below the programmed trigger level (for trigger tables a, b, and c) or when rece ive fifo is less than the trigger level minus the hysteresis value (for trigger tabl e d). this hysteresis value is the same as the auto rts hysteresis value in table 13 . table 6 below explains this when trigger table-b (see table 10 ) is selected. * after the trigger level is reached, an xoff character is se nt after a short span of time (= time required to send 2 characters); for example, after 2.083ms has el apsed for 9600 baud and 10-bit word length setting. 2.16 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fi fo along with normal incoming rx data. the 2850 compares each incoming receive character wi th xoff-2 data. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indica te detection of special character. although the internal register table shows xon, xoff registers with eight bits of character information, the actual number of bits is dependent on the programmed word lengt h. line control register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. bit-0 in the xon, xoff registers corresponds with the lsb bit for the receive character. 2.17 auto rs485 half-duplex control the auto rs485 half-duplex direction control changes the behavior of the transmitter when enabled by fctr bit-3. it de-asserts rts# output (high) following the last stop bit of the last character that has been transmitted. this helps in turning around the transcei ver to receive the remote st ation?s response. when the host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit fifo. the transmitter automatically re-asserts rts# output (low) prior sending the data. t able 6: a uto x on /x off (s oftware ) f low c ontrol rx t rigger l evel int p in a ctivation x off c haracter ( s ) s ent ( characters in rx fifo ) x on c haracter ( s ) s ent ( characters in rx fifo ) 8 8 8* 0 16 16 16* 8 24 24 24* 16 28 28 28* 24
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 18 2.18 infrared mode the 2850 uart includes the infrared encoder and decoder compatible to the irda (i nfrared data association) version 1.0. the irda 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide high- pulse for each ?0? bit in the transmit data stream. this signal encoding reduces the on- time of the infrared led, hence reduces the power consumption. see figure 12 below. the infrared encoder and decoder are enabled by setting m cr register bit-6 to a ?1?. when the infrared feature is enabled, the transmit data output, tx, idles at logic zero level. likewise, the rx input assumes an idle level of logic zero from a reset and power up, see figure 12 . typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the rx pin. each time it senses a light pulse, it returns a logic 1 to the data bit stream. however, this is not true with some infrared modules on the market which indicate a logic 0 by a light pulse. so the 2850 has a provision to invert the input polarity to accomodate this. in this case us er can enable fctr bit-2 to invert the input signal. f igure 12. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder- rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 19 2.19 sleep mode with auto wake-up the 2850 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. all of these conditions must be sati sfied for the 2850 to enter sleep mode: no interrupts pending for both channels of the 2850 (isr bit-0 = 1) sleep mode of both channels are enabled (ier bit-4 = 1) modem inputs are not toggling (msr bits 0-3 = 0) rx input pin of both channels are idling at a logic 1 the 2850 stops its crystal oscillator to conserve power in the sleep mode . user can check the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the 2850 resumes normal operation by any of the following: a receive data start bit transition (high to low) a data byte is loaded to the transmitter, thr or fifo a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the 2850 is awakened by any one of the above conditions, it will return to the sleep mode automatically after all interrupting conditions have been serviced and cleare d. if the 2850 is awakened by the modem inputs, a read to the msr is required to re set the modem inputs. in any case, t he sleep mode will not be entered while an interrupt is pending from channel a or b. t he 2850 will stay in the sleep mode of operation until it is disabled by setting ier bit-4 to a logic 0. if the address lines, data bus lines, iow#, ior#, csa#, csb#, and modem input lines remain steady when the 2850 is in sleep mode, the maximum current will be in the microamp range as specified in the dc electrical characteristics on page 38 . if the input lines are floating or are toggling while the 2850 is in sleep mode, the current can be up to 100 times more. if any of those signals are toggling or floating, then an external buffer would be required to keep the address, data and control lines steady to achieve the low current. a word of caution: owing to the star ting up delay of the crystal oscillato r after waking up from sleep mode, the first few receive characters may be lost. the number of ch aracters lost during the restart also depends on your operating data rate. more characters are lost when operati ng at higher data rate. also, it is important to keep rx a/b inputs idling high or ?mar king? condition during sleep mode to avoid receiving a ?break? condition upon the restart. this may occur when the external inte rface transceivers (rs-232, rs-485 or another type) are also put to sleep mode and cannot maintain the ?mar king? condition. to avoid this, the designer can use a 47k-100k ohm pull-up resistor on the rxa and rxb pins.
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 20 2.20 internal loopback the 2850 uart provides an intern al loopback capability for system di agnostic purposes . the internal loopback mode is enabled by setting mcr register bit-4 to logi c 1. all regular uart functions operate normally. figure 13 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx pin is held high or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ignored. caution: the rx input must be held high during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. f igure 13. i nternal l oop b ack in c hannels a and b txa/txb rxa/rxb modem / general purpose control logic internal data bus lines and control signals rtsa#/rtsb# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) ctsa#/ctsb# dtra#/dtrb# dsra#/dsrb# ria#/rib# cda#/cdb# op1# op2# rts# cts# dtr# dsr# ri# cd# vcc vcc op2a#/op2b#
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 21 3.0 uart internal registers each of the uart channel in the 2850 has its own set of configuration registers selected by address lines a0, a1 and a2 with csa# or csb# selecting the channel. the complete register set is shown on table 7 and table 8 . . t able 7: uart channel a and b uart internal registers a2,a1,a0 a ddresses r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - div latch low byte read/write lcr[7] = 1, lcr 0xbf 0 0 1 dlm - div latch high byte read/write 0 0 0 drev - device revision code read-only dll, dlm = 0x00, lcr[7] = 1, lcr 0xbf 0 0 1 dvid - device identification code read-only 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr[7] = 0 1 0 1 lsr - line status register reserved read-only write-only 1 1 0 msr - modem status register reserved read-only write-only 1 1 1 spr - scratch pad register read/write lcr[7] = 0, fctr[6] = 0 1 1 1 flvl - tx/rx fifo level counter register read-only lcr[7] = 0, fctr[6] = 1 1 1 1 emsr - enhanced mode select register write-only e nhanced r egisters 0 0 0 trg - tx/rx fifo trigger level reg fc - tx/rx fifo level counter register write-only read-only lcr = 0xbf 0 0 1 fctr - feature control reg read/write 0 1 0 efr - enhanced function reg read/write 1 0 0 xon-1 - xon character 1 read/write 1 0 1 xon-2 - xon character 2 read/write 1 1 0 xoff-1 - xoff character 1 read/write 1 1 1 xoff-2 - xoff character 2 read/write
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 22 t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0/ 0/ 0/ 0/ modem status int. enable rx line status - int. enable tx empty int. enable rx data int. enable cts# int. enable rts# int. enable xoff int.. enable sleep mode enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 int source bit-5 int source bit-4 0 1 0 fcr wr rx fifo trigger rx fifo trigger 0/ 0/ dma mode enable tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 1 1 lcr rd/wr divisor enable set tx break set parity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0/ 0/ internal lopback enable op2#/int output enable rsvd (op1#) rts# output control dtr# output control lcr[7] = 0 brg pres - caler ir mode enable xonany 1 0 1 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx fram - ing error rx parity error rx over - run error rx data ready 1 1 0 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 fctr[6]=0 1 1 1 emsr wr rsvd rsvd auto rts hyst. bit-3 auto rts hyst. bit-2 rsvd rsvd rx/tx fifo count rx/tx fifo count lcr[7] = 0 fctr[6]=1 1 1 1 flvl rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 lcr 0xbf 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 23 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 14. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 12. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive interr upts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. 0 0 0 drev rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 lcr 0xbf dll=0x00 dlm=0x00 0 0 1 dvid rd 0 0 0 1 0 0 1 0 enhanced registers 0 0 0 trg wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr=0 x bf 0 0 0 fc rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 fctr rd/wr rx/tx mode scpad swap trig ta b l e bit-1 trig ta b l e bit-0 auto rs485 direction control rx ir input inv. auto rts hyst bit-1 auto rts hyst bit-0 0 1 0 efr rd/wr auto cts enable auto rts enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5] soft- ware flow cntl bit-3 soft - ware flow cntl bit-2 soft - ware flow cntl bit-1 soft - ware flow cntl bit-0 1 0 0 xon1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 xoff1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 24 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; rese tting ier bits 0-3 enables the xr16c2850 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data character in th e non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. ? logic 0 = disable the receive data ready interrupt (default). ? logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty in the non- fifo mode or when data in the fifo fa lls below the programmed trigger level in the fifo mode. if the thr is empty when this bit is enabled , an interrupt will be generated. ? logic 0 = disable transmit ready interrupt (default). ? logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo . lsr bits 1-4 generate an interrupt immediately when the character has been received. ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr bit-4 = 1) ? logic 0 = disable sleep mode (default). ? logic 1 = enable sleep mode. see sleep mode section for complete details. ier[5]: xoff interrupt enable (requires efr bit-4=1) ? logic 0 = disable the software flow cont rol, receive xoff interrupt (default). ? logic 1 = enable the software flow control, receive xo ff interrupt. see software flow control section for details. ier[6]: rts# output interrupt enable (requires efr bit-4=1) ? logic 0 = disable the rts# interrupt (default). ? logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# pin makes a transition from low to high.
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 25 ier[7]: cts# input interrupt enable (requires efr bit-4=1) ? logic 0 = disable the cts# interrupt (default). ? logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt level to be se rviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 9 , shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by a 4-char plus 12 bits delay timer. ? txrdy is by tx trigger level or tx fifo empty (or transmitter empty in auto rs-485 control). ? msr is by any of the msr bits 0, 1, 2 and 3. ? receive xoff/special character is by det ection of a xoff or special character. ? cts# is when its transmitter toggles the input pin (fro m low to high) during auto cts flow control enabled by efr bit-7. ? rts# is when its receiver toggles the output pin (fro m low to high) during auto rts flow control enabled by efr bit-6. 4.4.2 interrupt clearing: ? lsr interrupt is cleared by a read to the lsr register. ? rxrdy interrupt is cleared by reading data until fifo fa lls below the trigger level. ? rxrdy time-out interrupt is cleared by reading rhr. ? txrdy interrupt is cleared by a read to the isr register or writing to thr. ? msr interrupt is cleared by a read to the msr register. ? xoff interrupt is cleared by a read to isr or when xon character(s) is received. ? special character interrupt is cleared by a read to isr or after the next character is received. ? rts# and cts# flow control interrupts are cleared by a read to the msr register. ] t able 9: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 1 1 0 0 rxrdy (receive data time-out) 3 0 0 0 1 0 0 rxrdy (received data ready) 4 0 0 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xoff or special character)
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 26 isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition). isr[5:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels (see table 9 ). see ?section 4.4.1, interrupt generation:? on page 25 and ?section 4.4.2, interrupt clearing:? on page 25 for details. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fi fos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default). ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. 7 1 0 0 0 0 0 cts#, rts# change of state - 0 0 0 0 0 1 none (default) t able 9: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 27 fcr[3]: dma mode select controls the behavior of the txrdy# and rxrdy# pins. see dma operation section for details. ? logic 0 = normal operation (default). ? logic 1 = dma mode. fcr[5:4]: transmit fifo trigger select (logic 0 = default, tx trigger level = 1) these 2 bits set the trigger level for the transmit fifo. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 10 below shows the selections. efr bit-4 must be set to ?1? before these bits can be accessed. note that the receiver and the transmitter cannot use different trigger tables. whichever selection is made last applies to both the rx and tx side. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) the fctr bits 5-4 are associated with these 2 bits. these 2 bits are used to set the trigger level for the receive fifo. the uart will issue a receive in terrupt when the number of the char acters in the fifo crosses the trigger level. table 10 shows the complete selections . note that the receiver and the transmitter cannot use different trigger tables. whichever selection is made last applies to both the rx and tx side. t able 10: t ransmit and r eceive fifo t rigger t able and l evel s election t rigger t able fctr b it -5 fctr b it -4 fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 r eceive t rigger l evel t ransmit t rigger l evel c ompatibility ta b l e - a 0 0 0 0 1 1 0 1 0 1 0 0 1 (default) 4 8 14 1 (default) 16c550, 16c2550, 16c2552, 16c554, 16c580 ta b l e - b 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 24 28 16 8 24 30 16c650a table-c 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 16c654 table-d 1 1 x x x x programmable via trg register. fctr[7] = 0. programmable via trg register. fctr[7] = 1. 16l2752, 16l2750, 16c2852, 16c850, 16c854, 16c864
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 28 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 11 for parity select ion summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the transmissi on while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format. bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8 bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 29 lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced (default). ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space?, low, state). this condition remains, un til disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition (default). ? logic 1 = forces the transmitter output (tx) to a ?space?, low, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers are selected. 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for controlling the serial/mod em interface signals or g eneral purpose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. ? logic 0 = force dtr# output high (default). ? logic 1 = force dtr# output low. mcr[1]: rts# output the rts# pin is a modem control output and may be us ed for automatic hardware flow control enabled by efr bit-6. the rts# output must be asserted before the auto rts can take effect. if the modem interface is not used, this output may be used as a general purpose output. ? logic 0 = force rts# output high (default). ? logic 1 = force rts# output low. if auto rts flow cont rol is enabled, it will take effect after this bit has been set. mcr[2]: reserved op1# is not available as an output pin on the 2850. but it is available for use during internal loopback mode. in the loopback mode, this bit is used to write the state of the modem ri# interface signal. t able 11: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0?
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 30 mcr[3]: op2# output / int output enable this bit enables and disables the operation of int, in terrupt output. if int output is not used, op2# can be used as a general purpose output. ? logic 0 = int (a-b) outputs disabled (three stat e mode) and op2# output is high (default). ? logic 1 = int (a-b) outputs enabled (a ctive mode) and op2# output is low. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 13 . mcr[5]: xon-any enable ? logic 0 = disable xon-any function (for 16c550 compat ibility, default). ? logic 1 = enable xon-any function. in this mode, any rx character rece ived will resume transmit operation. the rx character will be loaded into the rx fifo , unless the rx character is an xon or xoff character and the 2850 is programmed to use the xon/xoff flow control. mcr[6]: infrared encoder/decoder enable ? logic 0 = enable the standard modem receive an d transmit input/output interface (default). ? logic 1 = enable infrared irda receive and transmit inputs/outputs. the tx/rx output/input are routed to the infrared encoder/decoder. the data input and output levels conform to the irda infrared interface requirement. while in this mode, the infrared tx output will be low during idle data conditions. mcr[7]: clock prescaler select ? logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). ? logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one forth. 4.8 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. if ier bit-2 is set to a logic 1, an lsr interrupt will be generated immediately when any character in the rx fifo has an error (parity, framing, overrun, break). lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo (default). ? logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun error flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the er ror. if ier bit-2 is set, an interrupt will be generated immediately. lsr[2]: receive data parity error tag ? logic 0 = no parity error (default). ? logic 1 = parity error. the receive character in rhr does not have correct pa rity information and is suspect. this error is associated with the charac ter available for reading in rhr.
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 31 lsr[3]: receive data framing error tag ? logic 0 = no framing error (default). ? logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break error tag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx was a logic 0 for at least one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle condition, ?mark? or high. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to th e transmit shift register. t he bit is reset to logic 0 concurrently with the data loading to the transmit holding r egister by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bi t is set to a logic 1 whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears wh en there is no more error(s) in any of the bytes in the rx fifo. 4.9 modem status register (msr) - read only this register provides the current state of the modem interf ace input signals. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringi ng signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3).
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 32 msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7). auto cts flow control allows starting and stopping of local data transmissions based on the modem cts# signal. a high on the cts# pin will stop uart transmitte r as soon as the current character has finished transmission, and a low will re sume data transmission. normally ms r bit-4 bit is the complement of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status normally this bit is the complement of the dsr# input. in the loopback mode , this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status normally this bit is the complement of the ri# input. in the loopback mode th is bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status normally this bit is the complement of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 4.10 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the co ntent of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.11 enhanced mode select register (emsr) this register replaces spr (during a write) and is accessible only when fctr[6] = 1. emsr[1:0]: receive/transmi t fifo count (write-only) when scratchpad swap (fctr[6]) is asserted, emsr bits 1-0 controls what mode the fifo level counter is operating in. during alternate rx/tx fifo counter mode, the first value read after emsr bits 1-0 have been asserted will always be the rx fifo counter. the second value read will correspond wit h the tx fifo counter. the next value will be the rx fifo counter again, then t he tx fifo counter and so on and so forth. emsr[3:2]: reserved t able 12: s cratchpad s wap s election fctr[6] emsr[1] emsr[0] scratchpad is 0 x x scratchpad 1 0 0 rx fifo counter mode 1 0 1 tx fifo counter mode 1 1 0 rx fifo counter mode 1 1 1 alternate rx/tx fifo counter mode
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 33 emsr[5:4]: extended rts hysteresis emsr[7:6]: reserved 4.12 fifo level register (flvl) - read-only the fifo level register replaces the scratchpad regist er (during a read) when fctr[6] = 1. note that this is not identical to the fifo data count r egister which can be accessed when lcr = 0xbf. flvl[7:0]: fifo level register this register provides the fifo counter level for the rx fifo or the tx fifo or both depending on emsr[1:0]. see table 12 for details. 4.13 baud rate generator registers (dll and dlm) - read/write the concatenation of the contents of dlm and dll gives the 16-bit divisor value which is used to calculate the baud rate: ? baud rate = (clock frequency / 16) / divisor see mcr bit-7 and the baud rate table also. 4.14 device identification register (dvid) - read only this register contains the device id (0x12 for xr16c2 850). prior to reading this register, dll and dlm should be set to 0x00. 4.15 device revision register (drev) - read only this register contains the device revision information. for example, 0x01 means revision a. prior to reading this register, dll and dlm should be set to 0x00. t able 13: e xtended rts h ysteresis emsr b it -5 emsr b it -4 fctr b it -1 fctr b it -0 rts# h ysteresis (c haracters ) 0 0 0 0 0 0 0 0 1 4 0 0 1 0 6 0 0 1 1 8 0 1 0 0 8 0 1 0 1 16 0 1 1 0 24 0 1 1 1 32 1 0 0 0 40 1 0 0 1 44 1 0 1 0 48 1 0 1 1 52 1 1 0 0 12 1 1 0 1 20 1 1 1 0 28 1 1 1 1 36
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 34 4.16 trigger level / fifo data c ount register (trg) - write-only user programmable transmit/receive trigger level register. trg[7:0]: trigger level register these bits are used to program desired trigger levels wh en trigger table-d is selected. fctr bit-7 selects between programming the rx trigger level (a logic 0) and the tx trigger level (a logic 1). 4.17 fifo data count regi ster (fc) - read-only this register is accessible when lcr = 0xbf. note that th is register is not identical to the fifo level register which is located in the general regi ster set when fctr bit-6 = 1. fc[7:0]: fifo data count register transmit/receive fifo count. number of characters in transmit (fctr[7] = 1) or receive fifo (fctr[7] = 0) can be read via this register. 4.18 feature control regi ster (fctr) - read/write this register controls the xr16c2 850 new functions that are not ava ilable in st16c550 or st16c650a. fctr[1:0]: rts hysteresis user selectable rts# hysteresis levels for hardware flow control application. after reset, these bits are set to ?0? to select the next trigger leve l for hardware flow control. see ta b l e 13 for more details. fctr[2]: irda rx inversion ? logic 0 = select rx input as encoded irda data (idle state will be low). ? logic 1 = select rx input as inverted en coded irda data (idle state will be high). fctr[3]: auto rs-485 direction control this bit controls the func tionality of the rts# outp ut if hdcntl# is connected to vcc. if hdcntl# is connected to gnd, then the rts# output will function as the rs-485 half-duplex direction control signal. ? logic 0 = standard st16c550 mode. transmitter generates an interrupt when transmit holding register becomes empty and transmit shift register is shifting data out. ? logic 1 = enable auto rs485 direction control function. the direction control signal, rts# pin, changes its output logic state from low to high one bit time after the last stop bit of the last character is shifted out. also, the transmit interrupt generation is delayed until the transmitter shift register becomes empty. the rts# output pin will automatically return to a logic low when a data byte is loaded into the tx fifo. fctr[5:4]: transmit/receive trigger table select see ta b l e 10 for more details. fctr[6]: scratchpad swap ? logic 0 = scratch pad register is selected as genera l read and write register. st16c550 compatible mode. ? logic 1 = fifo count register (read-only), enhanced mode select register (write-only). number of characters in transmit or receive fifo can be read vi a scratch pad register when this bit is set. enhanced mode select register is select ed when it is written into. t able 14: t rigger t able s elect fctr b it -5 fctr b it -4 t able 0 0 table-a (tx/rx) 0 1 table-b (tx/rx) 1 0 table-c (tx/rx) 1 1 table-d (tx/rx)
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 35 fctr[7]: programmable trigger register select ? logic 0 = registers trg and fc selected for rx. ? logic 1 = registers trg and fc selected for tx. 4.19 enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide si ngle or dual consecutive character software flow control selection (see table 15 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[3:0]: software flow control select single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits. efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or over writing the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. ? logic 0 = modification disable/latch en hanced features. ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are saved to retain the user settings. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7are set to a logic 0 to be compatible with st16c550 mode (default). ? logic 1 = enables the above-mentioned register bits to be modified by the user. t able 15: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2, receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2, xoff1 and xoff2
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 36 efr[5]: special character detect enable ? logic 0 = special character detect disabled (default). ? logic 1 = special character detect enabled. the ua rt compares each incoming receive character with data in xoff-2 register. if a match exists, the receive data will be transfer red to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 co rresponds with the lsb bit of the receive character. if flow control is set for comparing xon1, xo ff1 (efr [1:0]= ?10?) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]= ?01?) then flow control works normally, but xoff2 will not go to the fifo, and will g enerate an xoff interrupt and a special character interrupt, if enabled via ier bit-5. efr[6]: auto rts flow control enable rts# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts is selected, an interrupt will be generated when the receive fifo is filled to the pr ogrammed trigge r level and rts de-asserts to a logic 1 at the next upper trigger level or h ysteresis level. rts# will re turn to a logic 0 when fifo data falls below the next lower tr igger level. the rts# output must be asserted (logic 0) before the auto rts can take effect. rts# pin will function as a gener al purpose ou tput when hardware flow control is disabled. ? logic 0 = automatic rts flow control is disabled (default). ? logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable automatic cts flow control. ? logic 0 = automatic cts flow control is disabled (default). ? logic 1 = enable automatic cts flow control. data tr ansmission stops when cts# input de-asserts to logic 1. data transmission resumes wh en cts# returns to a logic 0. 4.20 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write these registers are used as the prog rammable software flow control characters xoff1, xoff2, xon1, and xon2. for more details, see ta b l e 6 .
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 37 t able 16: uart reset conditions for channel a and b registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff emsr bits 7-0 = 0x00 flvl bits 7-0 = 0x00 efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 fc bits 7-0 = 0x00 i/o signals reset state tx high op2# high rts# high dtr# high rxrdy# high txrdy# low int three-state condition
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 38 test 1: the following inputs should remain steady at vcc or gnd state to minimize sleep current: a0-a2, d0-d7, ior#, iow#, csa# and csb#. also, rxa and rxb inputs must idle at logic 1 state while asleep. absolute maximum ratings power supply range 7 volts voltage at any pin gnd-0.3 v to 7 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data (margin of error: 15%) thermal resistance (48-tqfp) theta-ja =59 o c/w, theta-jc = 16 o c/w thermal resistance (44-plcc) theta-ja = 50 o c/w, theta-jc = 21 o c/w electrical characteristics dc electrical characteristics u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nits c onditions v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level (top mark date code of "dc yyww" and older) 2.4 vcc 3.0 vcc v v ihck clock input high level (top mark date code of "f2 yyww" and newer) 2.4 5.5 3.0 5.5 v v il input low voltage -0.3 0.8 -0.5 0.8 v v ih input high voltage (top mark date code of "dc yyww" and older) 2.0 vcc 2.2 vcc v v ih input high voltage (top mark date code of "f2 yyww" and newer) 2.0 5.5 2.0 5.5 v v olck clock output (xtal2) low voltage 0.4 0.4 v i ol = 6 ma i ol = 4 ma v ohck clock output (xtal2) high voltage 2.0 2.4 v i oh = -6 ma i oh = -1 ma v ol output low voltage see figure 14 . v oh output high voltage see figure 15 . i il input low leakage current 10 10 ua i ih input high leakage current 10 10 ua c in input pin capacitance 5 5 pf i cc power supply current 1.2 3 ma i sleep sleep current 30 100 ua see test 1
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 39 . . f igure 14. xr16c2850 vol s ink c urrent c hart f igure 15. xr16c2850 voh s ource c urrent c hart xr16c2850 sink current 0 2 4 6 8 10 12 14 16 18 20 22 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 vol (v) iol (ma) vcc=5v vcc=3.3v xr16c2850 source current 0 2 4 6 8 10 12 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 voh (v) ioh (ma) vcc=5v vcc=3.3v
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 40 ac electrical characteristics ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.90v to 5.5v, 70 p f l oad where applicable s ymbol p arameter l imits 3.3 m in m ax l imits 5.0 m in m ax u nit c onditions clk clock pulse duration 30 20 ns osc oscillator frequency 8 24 mhz osc external clock frequency 33 50 mhz tas address setup time 5 0 ns tah address hold time (top mark date code of "dc yyww" and older) 10 5 ns tah address hold time (top mark date code of "f2 yyww" and newer) 0 0 ns tcs chip select width 66 50 ns trd ior# strobe width 35 25 ns tdy read cycle delay 40 30 ns trdv data access time 35 25 ns tdd data disable time 0 25 0 15 ns twr iow# strobe width 40 25 ns tdy write cycle delay 40 30 ns tds data setup time 20 15 ns tdh data hold time 5 5 ns twdo delay from iow# to output 50 40 ns 100 pf load tmod delay to set interrupt from modem input 40 35 ns 100 pf load trsi delay to reset interrupt from ior# 40 35 ns 100 pf load tssi delay from stop to set interrupt 1 1 bclk trri delay from ior# to reset interrupt 45 40 ns 100 pf load tsi delay from stop to interrupt 45 40 ns tint delay from initial int re set to transmit start 8 24 8 24 bclk twri delay from iow# to reset interrupt 45 40 ns tssr delay from stop to set rxrdy# 1 1 bclk trr delay from ior# to reset rxrdy# 45 40 ns twt delay from iow# to set txrdy# 45 40 ns tsrt delay from center of start to reset txrdy# 8 8 bclk
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 41 trst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x or 8x of data rate hz f igure 16. c lock t iming f igure 17. m odem i nput /o utput t iming f or c hannels a & b ac electrical characteristics ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.90v to 5.5v, 70 p f l oad where applicable s ymbol p arameter l imits 3.3 m in m ax l imits 5.0 m in m ax u nit c onditions osc clk clk external clock iow # rts# dtr# cd# cts# dsr# int ior# ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state active active
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 42 f igure 18. d ata b us r ead t iming f igure 19. d ata b us w rite t iming t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# ior# d0-d7 rdtm t cs t rd 16write t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# iow# d0-d7 t cs t wr
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 43 f igure 20. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b f igure 21. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr) tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) (unloading) ier[1] enabled
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 44 f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b f igure 23. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo)
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 45 f igure 24. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b f igure 25. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b tx txrdy# iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si isr is read ier[1] enabled isr is read *int is cleared when the isr is read or when tx fifo fills up to the trigger level. tx txrdy# iow# int* d0:d7 s txdma d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri t (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level at least 1 empty location in fifo t srt tx fifo full t wt t si isr read isr read *int cleared when the isr is read or when tx fifo fills up to trigger level. ier[1] enabled
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 46 package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.039 0.047 1.00 1.20 a1 0.002 0.006 0.05 0.15 a2 0.037 0.041 0.95 1.05 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a 2 a 1 a seating plane l c
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 47 package dimensions (44 pin plcc) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.165 0.180 4.19 4.57 a1 0.090 0.120 2.29 3.05 a2 0.020 --- 0.51 --- b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.685 0.695 17.40 17.65 d1 0.650 0.656 16.51 16.66 d 2 0.590 0.630 14.99 16.00 d 3 0.500 typ. 12.70 typ. e 0.050 bsc 1.27 bsc h 1 0.042 0.056 1.07 1.42 h 2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 44 lead plastic leaded chip carrier (plcc) rev. 1.00 1 d d 1 a a 1 d d 1 d 3 b a 2 b 1 e seating plane d 2 244 d 3 c r 45 x h 2 45 x h 1
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 48 package dimensions (40 pin pdip) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.160 0.250 4.06 6.35 a1 0.015 0.070 0.38 1.78 a2 0.125 0.195 3.18 4.95 b 0.014 0.024 0.36 0.56 b1 0.030 0.070 0.76 1.78 c 0.008 0.014 0.20 0.38 d 1.98 2.095 50.29 53.21 e 0.600 0.625 15.24 15.88 e1 0.485 0.580 12.32 14.73 e 0.100 bsc 2.54 bsc ea 0.600 bsc 15.24 bsc eb 0.600 0.700 15.24 17.78 l 0.115 0.200 2.92 5.08 a 0 15 0 15 40 1 21 20 d e a 1 e 1 e a l seating plane a 2 b 1 b c e b e a
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos 49 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet november 2005. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. revision history date revision description february 2000 rev 1.0.0 initial datasheet. april 2002 rev 2.0.0 changed to standard style format. internal registers are described in the order they are listed in the internal register table. clarified timing diagrams. corrected auto rts hysteresis table. renamed rclk (receive clock) to bclk (baud clock) and tim - ing symbols. added t ah , t cs and osc. may 2004 rev 2.1.0 changed to single column format. added device status to ordering information. clarified sleep mode conditions. clarified pi n descriptions- changed from using logic 1 and logic 0 to high (vcc) and low (gnd) for input and output pin descriptions. added vol sink current and vo h source current charts ( figure 14 and figure 15 ). devices with top mark date code of "f2 yyww" and newer have 5v tolerant inputs (except for xtal1) and have 0 ns address hold time (t ah ). drev reg - ister was updated to 0x06. february 2005 rev 2.1.1 corrected datasheet to show that all inputs are 5v tolerant (including xtal1) in devices with top mark date code of "f2 yyww" and newer. august 2005 rev 2.1.2 removed discontinued 40-pin pdip from ordering information. november 2005 rev 2.1.3 corrected part numbers in ordering information.
xr16c2850 xr 2.97v to 5.5v dual uart with 128-byte fifos rev. 2.1.3 i table of contents general description ......... ................ ................ ................. .............. .............. ...........1 a pplications ............................................................................................................................... .................1 f eatures ............................................................................................................................... ......................1 f igure 1. xr16c2850 b lock d iagram ............................................................................................................................... .......... 1 f igure 2. p in o ut a ssignment ............................................................................................................................... ...................... 2 ordering information ............................................................................................................................... ..2 pin descriptions ............ ................ ................. ................ ................. ................ ...........3 1.0 product description ..................................................................................................... ................7 2.0 functional descriptions ................................................................................................. ............8 2.1 cpu interface ........................................................................................................... ................................... 8 f igure 3. xr16c2850 d ata b us i nterconnections ................................................................................................................. 8 2.2 device reset .... .............. .............. .............. .............. .............. .............. ........... ......... .................................... 8 2.3 device identification and revision ........... ........................................................................... ............... 8 2.4 channel a and b selection .... .............. .............. .............. .............. .............. ........... .......... ..................... 8 t able 1: c hannel a and b s elect ............................................................................................................................... ................ 9 2.5 channel a and b internal registers ................. .............. .............. .............. .............. ............. .......... 9 2.6 dma mode ................................................................................................................ ....................................... 9 t able 2: t able 2txrdy# and rxrdy# o utputs in fifo and dma m ode ................................................................................ 9 2.7 inta and intb ouputs .................................................................................................... .......................... 10 t able 3: inta and intb p ins o peration for t ransmitter ...................................................................................................... 10 t able 4: inta and intb p in o peration f or r eceiver ............................................................................................................. 10 2.8 crystal oscillator or external clock input ............ .............. .............. .............. .............. ....... 10 f igure 4. t ypical oscillator connections ............................................................................................................................... 10 2.9 programmable baud rate generat or ........... .............. .............. .............. .............. ............ ......... ... 11 f igure 5. e xternal c lock c onnection for e xtended d ata r ate .......................................................................................... 11 f igure 6. b aud r ate g enerator and p rescaler ..................................................................................................................... 11 t able 5: t ypical data rates with a 14.7456 mh z crystal or external clock ...................................................................... 12 2.10 transmitter ........ .............. .............. .............. .............. ........... ............ ........... .......... ................................. 12 2.10.1 transmit holding register (thr) - write only .......................................................................... ............. 12 2.10.2 transmitter operatio n in non-fifo mode ................................................................................ ................ 12 f igure 7. t ransmitter o peration in non -fifo m ode .............................................................................................................. 13 2.10.3 transmitter operation in fifo mode .................................................................................... ..................... 13 f igure 8. t ransmitter o peration in fifo and f low c ontrol m ode ..................................................................................... 13 2.11 receiver ............................................................................................................... ..................................... 14 2.11.1 receive holding register (rhr) - read-only ............................................................................ .............. 14 f igure 9. r eceiver o peration in non -fifo m ode .................................................................................................................... 14 f igure 10. r eceiver o peration in fifo and a uto rts f low c ontrol m ode ....................................................................... 15 2.12 auto rts (hardware) flow co ntrol ........... .............. .............. .............. .............. ........... ......... ...... 15 2.13 auto rts hysteresis ................................................................................................... ......................... 15 2.14 auto cts flow control .................................................................................................. .................... 16 f igure 11. a uto rts and cts f low c ontrol o peration ....................................................................................................... 16 2.15 auto xon/xoff (software) flow control .................................................................................. . 17 t able 6: a uto x on /x off (s oftware ) f low c ontrol ............................................................................................................... 17 2.16 special character detect .. ............. .............. .............. .............. .............. .............. ......... ................. 17 2.17 auto rs485 half-duplex control ........................................................................................ .......... 17 2.18 infrared mode ...... .............. .............. .............. .............. ........... ........... ............ .......... .............................. 18 f igure 12. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 18 2.19 sleep mode with auto wake-u p ............ .............. .............. .............. .............. ........... ........... ............. 19 2.20 internal loopback ..................................................................................................... ......................... 20 f igure 13. i nternal l oop b ack in c hannels a and b .............................................................................................................. 20 3.0 uart internal registers ................................................................................................. ..........21 t able 7: uart channel a and b uart internal registers............................................................................ .......... 21 t able 8: internal registers description. s haded bits are enabled when efr b it -4=1......................................... 22 4.0 internal register descriptions .......................................................................................... ...23 4.1 receive holding register (rhr) - read- only .. .............. .............. .............. ........... ............ .......... .. 23 4.2 transmit holding register (thr) - write-only ............................................................................ 23 4.3 interrupt enable register (ier ) - read/write .......... .............. .............. .............. .............. .......... .. 23 4.3.1 ier versus receive fifo interrupt mode operation ....................................................................... ...... 23 4.3.2 ier versus receive/transmit fifo polled mode operation ................................................................ 24
xr xr16c2850 rev. 2.1.3 2.97v to 5.5v dual uart with 128-byte fifos ii 4.4 interrupt status register (isr) - read-only ............................................................................. .. 25 4.4.1 interrupt generation: .................................................................................................. .................................... 25 4.4.2 interrupt clearing: .................................................................................................... ....................................... 25 t able 9: i nterrupt s ource and p riority l evel ....................................................................................................................... 25 4.5 fifo control register (fcr) - write-only ................................................................................ ..... 26 t able 10: t ransmit and r eceive fifo t rigger t able and l evel s election .......................................................................... 27 4.6 line control register (lcr) - read/write ................................................................................ ..... 28 t able 11: p arity selection ............................................................................................................................... ......................... 29 4.7 modem control register (mcr) or gene ral purpose outputs control - read/write 29 4.8 line status register (lsr) - read only .................................................................................. ......... 30 4.9 modem status register (msr) - read only ................................................................................. ... 31 4.10 scratch pad register (spr) - read/write ................................................................................ .... 32 4.11 enhanced mode select register (emsr) ................................................................................... ... 32 t able 12: s cratchpad s wap s election ............................................................................................................................... ..... 32 t able 13: e xtended rts h ysteresis ............................................................................................................................... ......... 33 4.12 fifo level register (flvl) - read-only ................................................................................. ........ 33 4.13 baud rate generator registers (dll and dlm) - read/write ....... ........... ............ ........... ..... 33 4.14 device identification register (dvid) - read only .................................................................... 3 3 4.15 device revision register (drev) - read only ............................................................................ .. 33 4.16 trigger level / fifo data co unt register (trg) - wr ite-only ......... .............. .............. ........ 34 4.17 fifo data count register (fc) - read-only .............................................................................. ... 34 4.18 feature control register (fctr) - read/write ....................................................................... 34 t able 14: t rigger t able s elect ............................................................................................................................... ................ 34 4.19 enhanced feature register (efr) ........................................................................................ .......... 35 t able 15: s oftware f low c ontrol f unctions ........................................................................................................................ 35 4.20 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write ................ 36 t able 16: uart reset conditions for channel a and b................................................................................ ............ 37 absolute maximum ratings ......... ................. ................ .............. .............. ............ 38 typical package thermal resistance data (margin of error: 15%) 38 electrical characteristics....... ................. ................ .............. .............. ............ 38 dc e lectrical c haracteristics .............................................................................................................. 38 f igure 14. xr16c2850 vol s ink c urrent c hart ................................................................................................................... 39 f igure 15. xr16c2850 voh s ource c urrent c hart ............................................................................................................. 39 ac e lectrical c haracteristics .............................................................................................................. 40 ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.90v to 5.5v, 70 p f l oad where applicable ............................................................................................................................... .................. 40 f igure 16. c lock t iming ............................................................................................................................... .............................. 41 f igure 17. m odem i nput /o utput t iming f or c hannels a & b ................................................................................................. 41 f igure 19. d ata b us w rite t iming ............................................................................................................................... ............. 42 f igure 18. d ata b us r ead t iming ............................................................................................................................... ............... 42 f igure 20. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b ......................................................... 43 f igure 21. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b ....................................................... 43 f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b........................................ 44 f igure 23. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b......................................... 44 f igure 24. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b ........................... 45 f igure 25. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b ............................ 45 package dimensions (48 pin tqfp - 7 x 7 x 1 mm ).................. ................ .............. 46 package dimensions (44 pin plcc ) ................. .............. .............. .............. ............ 47 package dimensions (40 pin pdip) . ................. .............. .............. .............. ............ 48 r evision h istory ............................................................................................................................... ....... 49 t able of c ontents .............. ................ ................ ................. ................ ................. ............ i

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